Wind River Technical Sessions at FTF 2010

Getting the Most out of the Freescale QorIQ P4080 Using Advanced Multi-core Techniques

Felix Baum
Networking Track
Wednesday, June 23, 4:15 p.m., Tuscany C

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Multi-core represents a major evolution in processor technology. As silicon design becomes more complex, so does the software that engineers need to use underlying hardware capabilities. This session will take you beyond the initial symmetric multiprocessing (SMP) vs. asymmetric multiprocessing (AMP) scenarios and highlights the truly multi-core, multi-OS advanced implementations on top of a new generation of processors such as the Freescale P4080. A comparison of these configurations will be presented along with a general list of things to consider when migrating from single-core devices to a new platform.

Leveraging the Wind River Hypervisor on QorIQ Processors

Tomas Evensen
Enabling Technologies Track
Tuesday, June 22, 11:30 a.m., Tuscany C

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Hypervisor and multi-core technologies are being leveraged to create higher-performing and more reliable devices while consolidating systems to reduce power and space. This session describes real use cases of Wind River Hypervisor, from single-core devices, such as multifunction printers running multiple operating systems, to the eight-core Freescale P4080 for high-speed packet processing networking applications. The discussion will cover how Wind River Hypervisor leverages the QorIQ hardware capabilities, information on hypervisor and packet processing performance, and an overview of the tools required to effectively debug and optimize a hypervisor-based system.

The Next Generation Carrier Grade Platform

Tomas Evensen
Networking Track
Tuesday, June 22, 4:15 p.m., Tuscany D

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The technologies and competencies needed to create and integrate the full software stack for a multi-core embedded network device need to be integrated to create a complete next-generation networking platform. This session covers experiences, challenges, and requirements to successfully optimize, integrate, and test a complete stack, including hardware, virtualization, operating systems, and middleware, all enabled by an integrated development environment. The role of the hypervisor and virtualization in a complete carrier grade platform for both data plane and control plane will be highlighted.

Debugging Multi-core Software Using a Virtual Platform

Ross Dickson
Enabling Technologies Track
Wednesday, June 23, 5:15 p.m., Tuscany F–H

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This talk will present how you use virtual platforms when debugging multi-core software. With a virtual platform, you gain unobtrusive tracing and inspection, globally synchronized stop of the entire system, perfect repeatability, and reverse execution. Hardware and software setups can be easily varied to provoke bugs. Program faults can be communicated perfectly using check-pointing, and with scripting, it is possible to perform automated smart tracing and debugging. To illustrate the debug techniques enabled by virtual platforms, we will use a few real case studies based on Freescale multi-core platforms.

Panel Discussion

Virtualization Technology from Low-Power Dual-Core to High-Performance Eight-Core Solutions and More

Tomas Evensen, Chief Technology Officer, Wind River
Networking Track
Tuesday, June 22, 10:30 a.m.–11:30 a.m., RC Ballroom Salon III

Wind River Sponsored Session

Architectural Exploration for Networking Devices Using Wind River Simics Virtual Platforms

Ross Dickson and Chad Margolin
Networking and Enabling Technologies Tracks
Wednesday, June 23, 2 p.m.–4 p.m., Del Lago 4

This technical discussion, using a combination of demonstrations, presentation, and group participation, explores how Wind River Simics virtual platforms can be used to analyze the impact of changes to the architecture of a networked system. We will demonstrate how a virtual platform is much more configurable than physical hardware (and available long before the hardware) and how it is possible to easily explore different system architecture scenarios, trading off hardware and software (e.g., the value of implementing a hardware accelerator for an algorithm, the number of processing cores a program can make use of, and the split of software across heterogeneous cores).